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Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
FEATURES
* 1 LVCMOS/LVTTL output, 15 output impedence * Crystal oscillator interface designed for 25MHz, 18pF parallel resonant crystal * Output frequency: 125MHz * VCO range: 560MHz to 680MHz * RMS phase jitter @ 125MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.48ps (typical) (3.3V) Offset Noise Power 100Hz ............... -97.8 dBc/Hz 1kHz .............. -124.6 dBc/Hz 10kHz .............. -132.5 dBc/Hz 100kHz .............. -131.1 dBc/Hz * Voltage supply modes: VDD/VDDA = 3.3V VDD/VDDA = 2.5V * -40C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS840021I is a Gigabit Ethernet Clock Generator and a member of the HiPerClocksTM HiPerClockSTM family of high performance devices from ICS. The ICS840021I uses a 25MHz crystal to synthesize 125MHz. The ICS840021I has excellent phase jitter performance, over the 1.875MHz - 20MHz integration range. The ICS840021I is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space.
ICS
BLOCK DIAGRAM
OE 25MHz XTAL_IN
PIN ASSIGNMENT
VDDA OE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VDD Q0 GND nc
OSC
XTAL_OUT
Phase Detector
VCO
/5
Q0
ICS840021I
/25 (fixed)
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
840021AGI
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REV. A MAY 19, 2005
Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
Type Power Input Input Pullup Description Analog supply pin. Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. Power supply ground. Single-ended clock output. LVCMOS/LVTTL interface levels. 15 output impedence. Core supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3, 4 5 6 7 8 Name VDDA OE XTAL_OUT, XTAL_IN nc GND Q0 VDD
Unused Power Output Power
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Output Impedance VDD, VDDA = 3.465V VDD, VDDA = 2.625V Test Conditions Minimum Typical 4 7 7 51 15 Maximum Units pF pF pF k
TABLE 3. CONTROL FUNCTION TABLE
Control Inputs OE 0 1 Output Q0 Hi-Z Active
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Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 65 10 Units V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 60 10 Units V V mA mA
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE OE Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.465V VDD = 2.625V VDD = 3.465V or 2.625V -150 2.6 1. 8 0.5 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 5 Units V V V V A A V V V
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information Section, "Output Load Test Circuit" diagrams.
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Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum Typical Fundamental 25 50 7 1 MHz pF mW Maximum Units
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions Minimum Typical 125 Integration Range: 1.875MHz to 20MHz 20% to 80% 200 48 0.48 500 52 Maximum Units MHz ps ps %
tjit(O)
tR / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot.
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 2.5V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time Test Conditions Minimum Typical 125 Integration Range: 1.875MHz to 20MHz 20% to 80% 250 48 0.50 550 52 Maximum Units MHz ps ps %
tjit(O)
tR / tF
odc Output Duty Cycle NOTE 1: Please refer to the Phase Noise Plot.
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REV. A MAY 19, 2005
Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 125MHZ (3.3V OR 2.5V)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110
Gigabit Ethernet Filter 125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz (3.3V) = 0.48ps (typical) 1.875MHz to 20MHz (2.5V) = 0.50ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
-120 -130 -140 -150 -160
100 1k 10k
-170 -180 -190
Phase Noise Result by adding Gigabit Ethernet Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
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REV. A MAY 19, 2005
Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5% 1.25V 5%
VDD, VDDA
SCOPE
Qx
VDD, VDDA
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V 5%
-1.25V 5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
80%
Phase Noise Mask
80% 20%
Clock Outputs
f1 Offset Frequency f2
20% tR tF
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
V
DD
Q0
t PW
t
2
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. A MAY 19, 2005
Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840021I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V or 2.5V VDD .01F 10
VDDA .01F 10F
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840021I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
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REV. A MAY 19, 2005
Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
output frequency. The C1 = 22pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy.
APPLICATION SCHEMATIC
Figure 3A shows a schematic example of the ICS840021I. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 25MHz crystal is used for generating 125MHz
VDD R2 10 C3
VDDA C4 0.1u U1 OE 1 2 3 4 VDDA OE XTAL_OUT XTAL_IN VDD Q0 GND NC 8 7 6 5 VDD Q R3 33 Zo = 50 Ohm
10uF
C2 33pF
X1 ICS840021I C1 22pF C5 0.1u LVCMOS
VDD=3.3V
FIGURE 3A. ICS840021I SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of ICS840021I P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed
in the Table 7. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane.
TABLE 7. FOOTPRINT TABLE
Reference C1, C2 C3 C4, C5 Size 0402 0805 0603
R2, R3 0603 NOTE: Table 7, lists component sizes shown in this layout example.
FIGURE 3B. ICS840021I PC BOARD LAYOUT EXAMPLE
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REV. A MAY 19, 2005
Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
TABLE 8. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS840021I is: 1961
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REV. A MAY 19, 2005
Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
8 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 9. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
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REV. A MAY 19, 2005
Integrated Circuit Systems, Inc.
ICS840021I
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR
Marking 021AI 021AI TBD TBD Package 8 lead TSSOP 8 lead TSSOP 8 lead "Lead-Free" TSSOP 8 lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 10. ORDERING INFORMATION
Part/Order Number ICS840021AGI ICS840021AGIT ICS840021AGILF ICS840021AGILFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840021AGI
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